Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a receiver circuit for receiving a data signal in a semiconductor device.
A typical semiconductor device includes a receiver circuit configured to receive an external data signal.
FIG. 1 is a block diagram illustrating a conventional circuit for receiving data in a semiconductor device.
Referring to FIG. 1, the receiver circuit includes a data buffering unit 10 and a data synchronization unit 20. The data buffering unit 10 is configured to buffer an external data signal DATA_SIG in a CMOS region based on a voltage level of a data reference signal DATA_REF, determine the logic level of the external data signal DATA_SIG, and amplify a swing width of the external data signal DATA_SIG. When the external data signal DATA_SIG is composed of 1 bit, the data synchronization unit 20 is configured to output buffered data signals BUF_DATA_SIG and /BUF_DATA_SIG, which are outputted from the data buffering unit 10, in synchronism with source clocks CLK and CLKB. When the external data signal DATA_SIG is composed of multi-bits which are serially inputted, the data synchronization unit 20 is configured to output the buffered data signals BUF_DATA_SIG and /BUF_DATA_SIG, which are outputted from the data buffering unit 10, in synchronism with multi-phase source clocks CLK and CLKB, such that the multi-bits are outputted in parallel.
For reference, when the external data signal DATA_SIG is composed of 2 bits which are serially inputted, the data synchronization unit 20 illustrated in FIG. 1 outputs the buffered data signals BUF_DATA_SIG and /BUF_DATA_SIG, which are outputted from the data buffering unit 10, in synchronism with the multi-phase source clocks CLK and CLKB, such that the 2 bits are outputted in parallel.
In the semiconductor device having the above-described configuration, variation in power supplied to the data buffering unit 10 and the data synchronization unit 20 may change the time taken until the data buffering unit 10 buffers the data signal DATA_SIG and outputs the buffered data signals BUF_DATA_SIG and /BUF_DATA_SIG.
That is to say, if the level of a power supply voltage (VDD) supplied to the data buffering unit 10 rises (i.e., the power supplied thereto becomes strong), the operating speed of the circuit included in the data buffering unit 10 becomes relatively faster than when normal power is supplied. Hence, the data signals BUF_DATA_SIG and /BUF_DATA_SIG buffered at a timing earlier than the timing at which the data signal DATA_SIG is applied are generated.
Conversely, if the level of the power supply voltage (VDD) supplied to the data buffering unit 10 drops (i.e., the power supplied thereto becomes weak), the operating speed of the circuit included in the data buffering unit 10 becomes relatively slower than when normal power is supplied. Hence, the data signals BUF_DATA_SIG and /BUF_DATA_SIG buffered at a timing later than the timing at which the data signal DATA_SIG is applied are generated.
In addition, the duty ratios of the buffered data signals BUF_DATA_SIG and /BUF_DATA_SIG outputted from the data buffering unit 10 are distorted.
In designing the data buffering unit 10, it is preferred that the duty ratios of the buffered data signals BUF_DATA_SIG and /BUF_DATA_SIG outputted at a specific target level of the power supply voltage (VDD) are matched with each other. However, if the level of the power supply voltage (VDD) is higher or lower than the specific target level, threshold voltages of transistors included in the data buffering unit 10 increase or decrease, causing distortion in the duty ratios of the buffered data signals BUF_DATA_SIG and /BUF_DATA_SIG.
Furthermore, if the data synchronization unit 20 is operated while receiving the buffered data signals BUF_DATA_SIG and /BUF_DATA_SIG whose generation timing is changed and whose duty ratios are distorted by the variation in the supplied power, it cannot precisely sample the buffered data signals BUF_DATA_SIG and /BUF_DATA_SIG in synchronism with the source clocks CLK and CLKB no matter how well it operates.
Moreover, in the data synchronization unit 20, a sampling point also changes according to the variation in the supplied power. Thus, it may be further impossible to precisely sample the buffered data signals BUF_DATA_SIG and /BUF_DATA_SIG.
As such, if the receiver circuit receives the data signal DATA_SIG applied when power noise occurs, a setup/hold time (tDSH) characteristic of the conventional semiconductor device is degraded, possibly causing the semiconductor device to malfunction.